The present invention relates to a semiconductor device and a method of manufacturing the same.
Recently, in semiconductor devices such as DRAM, the degree of integration has increased. As a result, the area occupied by a unit cell is reduced, while required capacitance must be maintained or increased. A method of securing sufficient cell capacitance within a limited area may include, for example, a method of using high-k material as a dielectric layer, a method of reducing the thickness of a dielectric layer, a method of increasing the effective area of a lower storage electrode, and so on. From among these methods, the method of using high-k material requires use of new equipment, while also guaranteeing reliability and mass production of dielectric layers. For these reasons, the method of increasing the effective area of a lower electrode is often used because the existing dielectric layer can be used without change and the process is relatively simple.
The method of increasing the effective area of a lower electrode may include a method of making the lower electrode in a 3-D form, such as a cylinder form or a fin form, a method of growing Hemispherical Grain (HSG) in the lower electrode, a method of increasing the height of the lower electrode, and the like. Among these methods, the method of growing HSG is difficult to apply to a semiconductor device subject to a design rule of 0.14 μm or less because a bridge may form between the lower electrodes. For this reason, to improve cell capacitance, the method of making the lower electrode in a 3-D form and the method of increasing the height of the lower electrode are widely used. Among them, the method of forming the lower electrode in a cylinder form or a stack form is most widely used.
FIG. 1 is a cross-sectional view illustrating a conventional semiconductor device.
Referring to FIG. 1, a capacitor 140, including lower electrodes 110, dielectric layers 120, and an upper electrode 130, is formed on a semiconductor substrate 100. Metal contact plugs 150 are coupled to both ends of the upper electrode 130.
The metal contact plugs 150 do not cause damage to an upper portion of the capacitor when the metal contact plugs 150 are formed, but are disadvantageous for applying voltage to a central portion of the capacitor. This is because the metal contact plugs 150 are coupled only to ends of the upper electrode 130. Since the metal contact plugs 150 are coupled to the ends of lower portions of the upper electrode 130, voltage must pass through the sidewalls of the upper electrode 130 in order to apply voltage to the entire upper electrode 130. There are disadvantages in that, when the voltage passes through the sidewalls of the upper electrode 130, resistance is generated and the desired level of voltage is not properly transferred to the entire upper electrode 130. Furthermore, contact resistance is great because the contact area of the metal contact plugs 150 and the upper electrode 130 is small.
FIG. 2 is a cross-sectional view illustrating another conventional semiconductor device.
Referring to FIG. 2, a capacitor 240, including lower electrodes 210, dielectric layers 220, and an upper electrode 230, is formed on a semiconductor substrate 200. Metal contact plugs 250 are coupled to the top of the upper electrode 230.
The metal contact plugs 250 coupled to the top of the upper electrode 130 can stably transfer voltage to a central portion of the capacitor 240. However, the upper portion of the capacitor 240 is likely to be damaged by the metal contact plugs 250. Also, contact resistance is great because the contact area of the metal contact plugs 250 and the upper electrode 230 is small.